Digital to analog conversion apparatus and method with cross-fading between new and old data

ABSTRACT

Most appropriate data of a plurality of level-converted digital data obtained by level conversion of the same input digital data by different conversion factors is selected based on a signal quality of each level-converted digital data. The other level-converted digital data is attenuated to or below a predetermined noise level. Switching between previously selected data and newly selected data is effected by cross-fading. The level-converted digital data are D/A converted to respective analog signals. Level conversion of the analog signals are carried out again based on respective corresponding ones of the conversion factors to restore a level of the input digital data, and all the level-converted analog signals are then added together. When an amplitude level of the input digital data exceeds a predetermined value, the cross-fading is started between the previously selected data and the newly selected data which are delayed by the predetermined amount of delay, and when during the cross-fading a larger rate of change in the amplitude level of the input digital data than a predetermined value is detected, the cross-fading is carried out at a rate larger than a predetermined rate in dependence on the rate of change in the amplitude level. In another form, the cross-fading is started at a first rate when the amplitude level exceeds a first predetermined value, and when during the cross-fading the amplitude level exceeds a second predetermined value larger than the first one, the cross-fading is carried out at a second rate larger than the first rate.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to D/A conversion apparatus and method of afloating type which perform level conversion of input digital data bydifferent conversion factors, converts the resulting data into analogdata, then restores the analog data to an original level of the inputdigital data, and carries out addition of the analog data, therebyachieving an increased dynamic range of the reproduced sound.

2. Prior Art

In recent years, the conversion accuracy of A/D converters has beenimproved by virtue of delta-sigma modulators of higher order, and withthis improvement, there is an increasing demand for further enhancementin the resolution and dynamic range of D/A converters. To meet thedemand, a D/A conversion apparatus of a floating type has beenconventionally developed which uses a D/A converter (hereinafterreferred to as the “DAC”) having a limited number of bits forconversion, and is capable of realizing a resolution and a dynamic rangeexceeding respective levels attainable by the limited number of bits forconversion. In this type of converter, when an N-bit (e.g. 20-bit) DACis used for carrying out D/A conversion of M-bit (M>N: e.g. 24-bit)digital data, if the digital data has P bits (M≧P>N) as effective bits,the digital data is directly subjected to D/A conversion without beingfurther processed, and M−N less significant bits (e.g. four lesssignificant bits) are truncated. On the other hand, if the input levelof the digital data lowers so that the effective word length of the sameis reduced to P′ bits (P′≧N), the digital data is converted into dataobtained by multiplying the same by a conversion factor of 2^(M−N), i.e.by shifting the original data toward MSB (most significant bit) by M−Nbits so that the M−N less significant bits have a value of zero, andthen the resulting level-converted data is subjected to D/A conversion.Whether input digital data is to be subjected to D/A conversion withoutbeing further processed or after being multiplied by the conversionfactor of 2^(M−N) is determined depending on whether an overflow of dataoccurs when the input digital data is shifted by M−N bits.

In the D/A conversion apparatus constructed as above, when input datahas P significant bits as effective bits, the length of word or bits forconversion is sufficiently large, so that the effect of the truncationof the M−N less significant bits is almost negligible (even if a problemoccurs due to the truncation, it can be solved e.g. by additionallycarrying out dithering as required). On the other hand, when theeffective bit length of input data is P′ bits, the data is multiplied bythe conversion factor of 2^(M−N), and the M−N less significant bitsthereof are truncated during the D/A conversion. Therefore, in thiscase, M−N less significant bits of the data which would be truncated ifthe data were not multiplied by the conversion factor of 2^(M−N) can beeffectively D/A converted, whereby an increased resolution and anincreased dynamic range are achieved. In the latter case, however, sincean analog signal output from the DAC also has a magnitude multiplied by2^(M−N), it is required to carry out a level adjustment by multiplyingthe analog output by 1/2^(M−N).

The D/A conversion apparatus of the floating type constructed as aboveincludes one which employs a single DAC and the gain of an amplifierthat amplifies an output from the single DAC is switched according tothe conversion factor by which the level of input digital data isconverted, and another which employs a plurality of DAC's that performD/A conversion of plural pieces of digital data obtained through levelconversion of input digital data by respective different conversionfactors, and one of the outputs from the DAC's which has been subjectedto the level conversion by the most appropriate conversion factor isselected (Japanese Patent Publication (Kokoku) No. 7-93579).

However, according to the former floating-type D/A conversion apparatus,since it is required to switch the gain of the analog amplifierinstantaneously according to the level of the digital data, the outputof the amplifier cannot follow up the switching, or DC offset of theamplifier can fluctuate, which can produce untoward noise which isaudible. The latter floating-type D/A conversion apparatus also switchesbetween analog signals output from the DAC's, so that transient noiseoccurs upon the switching. These problems are extremely seriousparticularly when the resolution of digital data to be subjected to D/Aconversion covers even a low noise range e.g. an SN ratio of 120 to 140dB which can be conventionally realized only by analog circuitry.

To solve these problems, the present assignee has already proposed, e.g.in Japanese Laid-Open Patent Publication (Kokai) No. 11-308109, a D/Aconversion apparatus of an advanced cross-fading algorithm type that iscapable of effectively preventing generation of noise upon the switchingbetween DAC's, by cross-fading the digital data in advance of theswitching. This D/A conversion apparatus generates only a very smallamount of noise upon the switching between the DAC's and is thereforecapable of realizing a high-accuracy D/A conversion, as well asachieving an improved dynamic range.

In this D/A conversion apparatus, the advanced cross-fading operation ismade possible by provision of a delay memory for delaying input digitaldata by a predetermined time period. To reduce the level of noise uponthe switching between the DAC's, it is preferred that the cross-fadingis carried out at a gentle cross-fading rate (by a small cross-fadingstep i.e., over a large number of cross-fading steps) or over asufficiently long time period. However, to realize such a gentleadvanced cross-fading without causing overflow and clipping of data evenwhen the level of the digital data steeply changes, the delay memory isrequired to provide a large amount of delay, which leads to an increasedsize of hardware, and hence to an increased manufacturing cost. Further,such an increase in the amount of delay results in a perceivableauditory delay, particularly when the D/A conversion apparatus isapplied to a mixer that processes data of live sounds, or the like.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a D/A conversionapparatus and a D/A conversion method of a floating type which are notonly capable of low-noise and high-dynamic range D/A conversion but alsocapable of carrying out the advanced cross-fading at a cross-fading ratesufficiently gentle for practical use by using a delay memory having asmall amount of delay.

To attain the above object, according to a first aspect of theinvention, there is provided a D/A conversion apparatus comprising adigital signal processor that carries out level conversion of same inputdigital data by different conversion factors into a plurality oflevel-converted digital data, selects and outputs most appropriate dataof the plurality of level-converted digital data based on a signalquality of each of the plurality of level-converted digital data,outputs other data of the plurality of level-converted digital dataafter attenuating the other data to or below a predetermined noiselevel, and switches between data previously selected as the mostappropriate data and data newly selected as the most appropriate data bycarrying out cross-fading between the previously selected data and thenewly selected data, a plurality of D/A converters that carry out D/Aconversion of the plurality of level-converted digital data output fromthe digital signal processor to respective analog signals and outputsthe analog signals, and an analog adder device that carries out levelconversion of the analog signals output from the plurality of D/Aconverters again based on respective corresponding ones of theconversion factors in a manner such that resulting analog signals have alevel corresponding to a level of the input digital data, and then addstogether all of the level-converted analog signals.

The D/A conversion apparatus according to the first aspect of theinvention is characterized in that the digital signal processorcomprises a cross-fading section that carries out cross-fading betweenthe previously selected data and the newly selected data, a delaysection that delays the input digital data by a predetermined amount ofdelay which is shorter than a time period required for completion of thecross-fading carried out at a predetermined cross-fading rate by thecross-fading section, and a cross-fading control section that controlsthe cross-fading section such that when an amplitude level of the inputdigital data exceeds a predetermined threshold value, the cross-fadingsection starts the cross-fading at the predetermined cross-fading ratebetween the previously selected data and the newly selected data whichare delayed by the predetermined amount of delay by the delay section,and that when during the cross-fading a rate of change in the amplitudelevel of the input digital data, which is larger than a predeterminedrate of change, is detected, the cross-fading section carries out thecross-fading at a cross-fading rate larger than the predeterminedcross-fading rate in dependence on the rate of change in the amplitudelevel of the input digital data.

According to this D/A conversion apparatus, when the amplitude level ofthe input digital data is increasing or decreasing, cross-fading(advanced cross-fading) is carried out between level-converted digitaldata based on a predetermined amount of delay shorter than a time periodrequired for completion of the cross-fading carried out at apredetermined cross-fading rate. When the amplitude level of the inputdigital data increases at a gentle rate, the cross-fading is completedin the time period required for completion of the cross-fading withoutcausing an overflow or clipping of data. Further, it is determinedwhether or not that a rate of change in the amplitude level of the inputdigital data is larger than a predetermined rate, and when it isdetermined that the rate of change in the amplitude level of the inputdigital data is larger than the predetermined rate, the cross-fadingrate is increased in dependence on the rate of change in the amplitudelevel, such that an overflow or clipping of selected level-converteddigital data can be prevented.

According to this D/A conversion apparatus, while the cross-fading canbe carried out at a sufficiently gentle cross-fading rate for preventionof noise due to gain discrepancies upon switching between gains, theamount of delay provided by the delay section can be sufficientlyreduced. This makes it possible to reduce the capacity of the delaymemory to simplify the construction of the apparatus and reduce themanufacturing cost. Further, the cross-fading coefficient can be changedin a manner adapted to a larger rate of change in the amplitude level ofthe input digital data. In this case, the noise-eliminating effect bythe cross-fading is degraded. However, since the input signal itself israpidly changing, the auditory masking effect makes the noisepractically imperceptible.

To attain the above object, according to a second aspect of theinvention, there is provided a D/A conversion apparatus comprising adigital signal processor that carries out level conversion of same inputdigital data by different conversion factors into a plurality oflevel-converted digital data, selects and outputs most appropriate dataof the plurality of level-converted digital data based on a signalquality of each of the plurality of level-converted digital data,outputs other data of the plurality of level-converted digital dataafter attenuating the other data to or below a predetermined noiselevel, and switches between data previously selected as the mostappropriate data and data newly selected as the most appropriate data bycarrying out cross-fading between the previously selected data and thenewly selected data, a plurality of D/A converters that carry out D/Aconversion of the plurality of level-converted digital data output fromthe digital signal processor to respective analog signals and outputsthe analog signals, and an analog adder device that carries out levelconversion of the analog signals output from the plurality of D/Aconverters again based on respective corresponding ones of theconversion factors in a manner such that resulting analog signals have alevel corresponding to a level of the input digital data, and then addstogether all of the level-converted analog signals.

The D/A conversion apparatus according to the second aspect of theinvention is characterized in that the digital signal processorcomprises a cross-fading section that carries out cross-fading betweenthe previously selected data and the newly selected data, a delaysection that delays the input digital data by a predetermined amount ofdelay which is shorter than a time period required for completion of thecross-fading carried out at a first predetermined cross-fading rate bythe cross-fading section, and a cross-fading control section thatcontrols the cross-fading section such that when an amplitude level ofthe input digital data exceeds a first predetermined threshold value,the cross-fading section starts the cross-fading at the firstpredetermined cross-fading rate between the previously selected data andthe newly selected data which are delayed by the predetermined amount ofdelay by the delay section, and that when during the cross-fading theamplitude level of the input digital data exceeds a second predeterminedthreshold value larger than the first predetermined threshold value, thecross-fading section carries out the cross-fading at a secondpredetermined cross-fading rate larger than the first predeterminedcross-fading rate.

The D/A conversion apparatus according to the second aspect of theinvention provides the same effects as obtained by the D/A conversionapparatus according to the first aspect of the invention.

Preferably, the second predetermined threshold value is set to a limitof the amplitude level of the input digital data beyond which anoverflow occurs when level conversion is carried out on the inputdigital data by a corresponding one of the different conversion factors,and the second cross-fading rate is set such that the cross-fading iscompleted in a time period corresponding to the predetermined amount ofdelay provided by the delay section.

According to this preferred embodiment, it is possible to secure alonger time period for the cross-fading at the first cross-fading rate,and at the same time, the second cross-fading rate can be set to aslowest rate within the limit defined by the predetermined amount ofdelay.

More preferably, the cross-fading is carried out using a cross-fadingcoefficient, the time period required for completion of the cross-fadingcarried out at the first predetermined cross-fading rate is a timeperiod required for processing of N1 samples of the input digital data,and the predetermined amount of delay provided by the delay sectioncorresponds to a time period required for processing of N2 samples ofthe input digital data (N1>N2). The cross-fading coefficient isincremented/decremented by 1/N1 for each step of the cross-fading, afterthe amplitude level of the input digital data exceeds the firstthreshold value and before the amplitude level of the input digital dataexceeds the second predetermined threshold value, and the cross-fadingcoefficient is incremented/decremented by (1−K)/N2 for each step of thecross-fading, after the amplitude level of the input digital dataexceeds the second predetermined threshold value, wherein K represents avalue of the cross-fading coefficient assumed at a time point theamplitude level of the input digital data exceeds the second thresholdvalue.

To attain the above object, according to a third aspect of theinvention, there is provided a D/A conversion method comprising thesteps of: delaying input digital data by a predetermined amount of delaywhich is shorter than a time period required for completion ofcross-fading carried out at a predetermined cross-fading rate; carryingout level conversion of the delayed input digital data by differentconversion factors into a plurality of level-converted digital data;selecting and outputting most appropriate data of the plurality oflevel-converted digital data based on a signal quality of each of theplurality of level-converted digital data, and outputting other data ofthe plurality of level-converted digital data after attenuating theother data to or below a predetermined noise level; switching betweendata previously selected as the most appropriate data of the pluralityof level-converted digital data and data newly selected as the mostappropriate data by carrying out the cross-fading between the previouslyselected data and the newly selected data; carrying out D/A conversionof the plurality of level-converted digital data to respective analogsignals and outputting the analog signals; and carrying out levelconversion of the analog signals again based on respective correspondingones of the conversion factors in a manner such that resulting analogsignals have a level corresponding to a level of the input digital data,and then adding together all of the level-converted analog signals;wherein when an amplitude level of the input digital data exceeds apredetermined threshold value, the cross-fading is started between thepreviously selected data and the newly selected data which are delayedby the predetermined amount of delay, and when during the cross-fading arate of change in the amplitude level of the input digital data, whichis larger than a predetermined rate of change, is detected, thecross-fading is carried out at a cross-fading rate larger than thepredetermined cross-fading rate in dependence on the rate of change inthe amplitude level of the input digital data.

The D/A conversion method according to the third aspect of the inventionprovides the same effects as obtained by the D/A conversion apparatusaccording to the first aspect of the invention.

To attain the above object, according to a fourth aspect of theinvention, there is provided a D/A conversion method comprising thesteps of: delaying input digital data by a predetermined amount of delaywhich is shorter than a time period required for completion ofcross-fading carried out at a first predetermined cross-fading rate;carrying out level conversion of the delayed input digital data bydifferent conversion factors into a plurality of level-converted digitaldata; selecting and outputting most appropriate data of the plurality oflevel-converted digital data based on a signal quality of each of theplurality of level-converted digital data, and outputting other data ofthe plurality of level-converted digital data after attenuating theother data to or below a predetermined noise level; switching betweendata previously selected as the most appropriate data of the pluralityof level-converted digital data and data newly selected as the mostappropriate data by carrying out the cross-fading between the previouslyselected data and the newly selected data; carrying out D/A conversionof the plurality of level-converted digital data to respective analogsignals and outputting the analog signals; and carrying out levelconversion of the analog signals again based on respective correspondingones of the conversion factors in a manner such that resulting analogsignals have a level corresponding to a level of the input digital data,and then adding together all of the level-converted analog signals;wherein when an amplitude level of the input digital data exceeds afirst predetermined threshold value, the cross-fading is started at thefirst predetermined cross-fading rate between the previously selecteddata and the newly selected data which are delayed by the predeterminedamount of delay, and when during the cross-fading the amplitude level ofthe input digital data exceeds a second predetermined threshold valuelarger than the first predetermined threshold value, the cross-fading iscarried out at a second predetermined cross-fading rate larger than thefirst predetermined cross-fading rate.

The D/A conversion method according to the fourth aspect of theinvention provides the same effects as obtained by the D/A conversionapparatus according to the second aspect of the invention.

The above and other objects, features and advantages of the inventionwill become more apparent from the following detailed description takenin conjunction of the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram showing the construction of a D/A conversionapparatus according to an embodiment of the present invention;

FIG. 2 is a timing chart which is useful in explaining the operation ofthe D/A conversion apparatus of FIG. 1;

FIG. 3A is a timing chart which is useful in explaining the operation ofthe D/A conversion apparatus of FIG. 1 in further detail;

FIG. 3B is a timing chart similar to FIG.3A;

FIG. 3C is a timing chart similar to FIG.3A;

FIG. 4 is a block diagram showing the construction of a cross-fadingcontrol section within a DSP of the D/A conversion apparatus of FIG. 1;

FIG. 5 is a flowchart showing a coefficient-calculating process executedby the cross-fading control section of the D/A conversion apparatus ofFIG. 1; and

FIG. 6 is a circuit diagram showing the construction of a D/A converteraccording to another embodiment of the invention.

DETAILED DESCRIPTION

The present invention will now be described in detail with reference todrawings showing preferred embodiments thereof.

FIG. 1 shows the whole arrangement of a D/A conversion apparatusaccording to an embodiment of the present invention.

This apparatus is comprised of two D/A conversion systems, i.e. a firstD/A conversion system provided with a first DAC 1 having an N-bitconversion accuracy and a second D/A conversion system provided with asecond DAC 2 also having an N-bit (e.g. 24-bit) conversion accuracy. Atan upstream stage of the DAC's, there is arranged a digital signalprocessing circuit, or more specifically, a digital signal processor(hereinafter referred to as “the DSP”) 3. The DSP 3 is comprised of adelay circuit 11 for delaying input digital data Di having M (e.g. 27)(M>N) effective bits as a common input by a predetermined time period TS(a time period required for processing e.g. 16 samples of data), amultiplier 12 connected to the delay circuit 11, for multiplying anoutput from the delay circuit 11 by a factor of k and supplying the sameto the DAC 1, another multiplier 13 connected to the delay circuit 11,for directly passing an output from the delay circuit 11 therethrough tothe DAC 2, and a pair of cross-faders 14, 15 interposed, respectively,between the multiplier 12 and the DAC 1 and between the multiplier 13and the DAC 2, which serve as digital attenuation means for selectivelyattenuating the outputs from the respective multipliers 12, 13 to avalue equal to or lower than a noise level of the DAC 1 or 2 as well asfor multiplying the outputs by respective coefficients K1, K2 (K1+K2=1)so as to carry out cross-fading when switching is carried out betweenthe outputs to be attenuated. Further, the DSP 3 includes a cross-fadingcontrol block 16 which is connected to the cross-faders 14, 15, as wellas to an analog attenuator circuit 5, referred to hereinafter. Thecross-fading control block 16 senses a level of the input digital dataDi to compare the same with two predetermined threshold values, i.e. afirst threshold value TH-Y and a second threshold value TH-R, and thencontrols the switching of the cross-faders, 14, 15 and the operation ofthe analog attenuator circuit 5.

When the amplitude level of the input digital data Di is equal to orlower than the first threshold value TH-Y, i.e., if the level of theinput data Di does not exceed the maximum amplitude that can beexpressed by N bits, the cross-fading control block 16 sets thecoefficients K1 and K2 to 1 and 0, respectively, whereas if theamplitude level of the input digital data Di rises above or exceeds thefirst threshold value TH-Y, the cross-fading control block 16 controlsthe cross-faders 14, 15 such that they start cross-fading at apredetermined cross-fading rate, and if the same exceeds the secondthreshold value TH-R, it controls the cross-faders 14, 15 such that thecross-fading operation is completed in a time period required forprocessing 16 samples of data stored in the delay circuit 11, andthereafter the coefficients K1 and K2 are held at 0 and 1, respectively.

An analog signal Vo1 output from the DAC 1 is attenuated by the factorof 1/k by an attenuater 6 connected thereto and then input to one inputof an analog adder 4, while an analog signal Vo2 output from the DAC 2is input as it is, to the other input of the analog adder 4 via theanalog attenuator circuit 5. The analog adder 4 may be implemented by aninverting amplifier comprised of an operational amplifier 21, a feedbackresistance 22, and input resistances 23, 24, and adds the analog inputsignals Vo1/k and Vo2. The analog attenuator circuit 5 is connectedbetween the DAC 2 and the analog adder 4. The analog attenuator circuit5 may be implemented by a low-pass filter circuit comprised of an analogswitch 31 which is connected to the cross-fading control block 16 andhaving one end thereof grounded, and which is turned on in response toan attenuation-instructing signal AT output from the cross-fadingcontrol block 16 before the DAC 2 starts to receive digitally attenuateddata i.e. data of “0” from the cross-fader 15, a resistance 32 connectedto the other end of the switch 31, a resistance 33 connected to the DAC2, and a capacitor 34 connected between the resistances 33 and 34 with ajunction of the capacitor 34 with the resistance 33 connected to theinput resistance 24 of the analog adder 4.

The output Vo from the analog adder 4 in the D/A conversion apparatusconfigured as above is expressed by the following equation (1):

Vo=Vo 1 /k+Vo 2  (1)

If original conversion outputs from the respective DAC's 1, 2 obtainedwhen the digital data Di is input are represented respectively byDAC1(Di) and DAC2(Di), and residual noises by VN1 and VN2, the outputsVo1 and Vo2 from the respective DAC's 1, 2 are expressed by thefollowing equations (2a) and (2b), respectively:

Vo 1 =k×DAC 1(Di)+VN 1  (2a)

Vo 2=DAC 2(Di)+VN 2  (2b)

Consequently, the output Vo from the analog adder 4 is expressed by thefollowing equation (3):

Vo=DAC 1(Di)+DAC 2(Di)+VN 1 /k+VN 2  (3)

Here, the DSP 3 selects one of the conversion outputs DAC1(Di) andDAC2(Di) which consists of more effective bits without an overflow, i.e.which can ensure a more excellent signal quality, and therefore theoutput Vo is further expressed by the following equation (4):

Vo=DAC(Di)+VN 1 /k+VN 2  (4)

As is apparent from the equation (4), the noise VN1 output from the DAC1 is reduced to 1/k, whereas the noise VN2 from the DAC 2 is notreduced, so that the noise floor is determined by the residual noise inthe DAC 2. Now, let it be assumed that digital data that is input isformed of 27 bits (M=27) and the DAC's 1, 2 each have a 24-bitconversion accuracy (N=24), i.e. are capable of converting 24 bits. Inthis case, when the DAC 2 is in operation, since no more than 24 bits ofthe entire data can be converted, it is impossible to reduce the noisefloor to less than a value corresponding to the dynamic range of 144 dB.On the other hand, when the DAC 1 is in operation, it is possible toconvert the entire 27-bit data, and therefore the dynamic range can beincreased to the proper dynamic range of 162 dB. However, if theresidual noise from the DAC 2 is added, it is impossible to reduce thenoise floor to less than the value corresponding to the dynamic range of144 dB. To solve this problem, in the apparatus according to the presentembodiment, when the DAC 1 is selected for operation, theattenuation-instructing signal AT is delivered to the analog attenuatorcircuit 5 to turn it on. As a result, the noise floor during theoperation of the DAC 1 is reduced, whereby the dynamic range isincreased to the proper dynamic range of 162 dB.

If the input impedance of the operational amplifier 21 changes independence on whether the analog attenuator circuit 5 is ON or OFF, thegain of the analog adder 4 changes, which causes fluctuation in outputoffset voltage of the operational amplifier 21. In general, the amountof offset variation at the output of an operational amplifier isapproximately 0.5 mV, which is a very large value when considered incomparison with the resolution of a DAC, which has a noise level ofseveral μvolts (in a 24-bit DAC, 1 LSB 0.6 μVRMS). To solve the problem,according to the present embodiment, the analog attenuator circuit 5 isformed of a low-pass filter circuit for attenuating only medium-to-highfrequency range components of the analog signal from the DAC 2, wherebythe direct current input impedance of the analog adder 4 is preventedfrom fluctuating due to the ON/OFF operations of the analog attenuatorcircuit 5.

Referring to FIG. 2, there are shown changes in the level of inputdigital signal Di and the level of the attenuation-instructing signal ATtogether with timing of switching performed between the DAC's 1, 2within the DSP 3.

Switching between the DAC's 1, 2 is carried out in a progressive manner,i.e., through cross-fading so as to prevent transient distortion of theoutput analog signal, insufficient response to the input digital signal,and occurrence of hop noise, etc. In the following, the cross-fadingcarried out in switching from the DAC 1 to the DAC 2 cases will bemainly described.

First, in the case of switching from the DAC 1 to the DAC 2, as shown inFIG. 2, when the amplitude level of the input digital data Di exceedsthe first threshold value TH-Y at a time point t2, the cross-facing isstarted at a time point t1 earlier than the time point t2 by a timeperiod TS corresponding to a processing time of 16 samples of datastored in the delay circuit 11. During the cross-fading, thecross-fading coefficients K1, K2 are changed at a first predeterminedcross-fading rate, e.g. 1/128 per step. Then, if the cross-fading is notcompleted at a time point t3 the amplitude level of the input digitaldata Di exceeds the second threshold value TH-R, the cross-fading iscontinued at a second cross-fading rate such that the cross-fading iscompleted in a time period required for processing 16 samples of datacurrently stored in the delay circuit 11.

FIGS. 3A to 3C show timing charts useful in explaining the cross-fadingoperation in further detail.

FIG. 3A shows a case in which the amplitude level of the input digitaldata Di changes at a gentle rate, and the number X of samples of theinput digital data Di processed between the time point t2 the amplitudelevel exceeds the first threshold value TH-Y and the time point t3 thesame exceeds the second threshold value TH-R is equal to or more than128. In this case, at or before the time point t3 the amplitude level ofthe input digital data Di exceeds the second threshold value TH-R, thecross-fading of data delivered from the delay circuit 11, which isstarted at the time point t1 earlier than the time point t2 by the timeperiod TS, is completed, so that the whole cross-fading process iscompleted over 128 steps, i.e. carried out at the first cross-fadingrate KS=1/128 per step.

FIG. 3B shows a case in which the amplitude level of the input digitaldata Di rises at a steep rate. In the illustrated example, the number Xof samples of the input digital data Di processed between a time pointt12 the amplitude level exceeds the first threshold value TH-Y and atime point t13 the same exceeds the second threshold value TH-R is equalto 1. In this case, the cross-fading is carried out on one sample ofdata at the first cross-fading rate KS=1/128 per step, starting at atime point t10 earlier than the time point t12 by the time period TS,but the amplitude level of the input digital data Di immediately exceedsthe second threshold value TH-R, and hence the cross-fading rate ischanged to the second cross-fading rate KS=(1−1/128)/16 per step, tocarry out a rapid cross-fading operation starting at a time point t11earlier than the time point t13 by the time period TS, whereby thecross-fading is completed before the level of the input digital data Diexceeds the second threshold value TH-R, so that clipping of data can beprevented. It should be noted that due to the rapid cross-fading, thegain difference or discontinuity partially becomes noticeable togenerate a certain level of switching noise. However, since the inputdigital data Di itself undergoes a rapid change, the auditory maskingeffect makes the noise practically imperceptible.

FIG. 3C shows a case in which the number X of samples of the inputdigital data Di processed between a time point t21 the amplitude levelexceeds the first threshold value TH-Y and a time point t23 the sameexceeds the second threshold value TH-R is larger than 1 but smallerthan 128 (1<X<128). First, the cross-fading rate KS is set to the firstcross-fading rate 1/128 per step, and the cross-fading is started from atime point t20 earlier than the time point t21 by the time period TScorresponding to the capacity (16 samples) of the delay circuit 11. Theinput digital data Di exceeds the second threshold value TH-R only aftera certain considerable time period during which the cross-fading iscontinued at the cross-fading rate of 1/128 per step. Thus, during thistime period, the cross-fading is carried out at a gentle cross-fadingrate, i.e. by a small cross-fading step, so that noise is hardlygenerated. Thereafter, when the input digital data Di exceeds the secondthreshold value TH-R, the cross-fading rate KS is changed to the secondcross-fading rate of (1−K11)/16 per step, wherein K11 designates a valueof the cross-fading coefficient K2 assumed at the time of change of thecross-fading rate.

The above-described method of the cross-fading makes it possible toreduce the capacity of the memory of the delay circuit 11 by minimizingthe amount of delay to be provided by the delay circuit 11. Further,appropriate cross-fading can be carried out. in a manner properlyresponsive to changes in the amplitude level of the input digital dataDi.

Next, when the DAC 2 is switched over to the DAC 1, as shown in FIG. 2,the switching is not immediately carried out even when the amplitudelevel of the input digital data Di becomes lower than the firstthreshold value TH-Y, but the switching is carried out only when theamplitude level remains lower than the first threshold value TH-Y evenafter the lapse of a predetermined hold time HT. This prevents frequentswitching of the DAC's in response to a large-amplitude signal whichonly regularly crosses the zero level, and generation of noisesresulting from such unnecessary switching operations.

It should be note that if the difference (M−N) in the signal qualitybetween the DAC's 1 and 2 is 3 bits, the second threshold value TH-R maybe set to −18 dB corresponding to the 3 bits, but, to provide somemargins, the first threshold value TH-Y may be set to −24 dB, and thesecond threshold value TH-R to −19 dB.

FIG. 4 shows an example of the construction of the cross-fading controlblock 16 realizing the above described control operations.

The input digital data Di is input to level detectors 41, 42, where itis determined whether or not the amplitude level of the input digitaldata Di exceeds the first threshold value TH-Y and the second thresholdvalue TH-R, respectively. A cross-fading rate changeover section 43connected to the level detector 41, 42 is controlled by detection resultsignals Y, R delivered therefrom. The cross-fading rate changeoversection 43 is also supplied with cross-fading rates KSY (1/128), KSR(K/16) from cross-fading rate supply section 44, 45. The cross-fadingrate changeover section 43 selects the cross-fading rate KSY only whenthe detection result signal Y alone is made active, and selects thecross-fading rate KSR when the detection result signals Y. R are bothmade active. The cross-fading coefficient KS selected by thecross-fading switchover section 43 is input to a negative input terminalof an adder circuit 46 at a next stage. The adder circuit 46 has apositive input terminal thereof supplied with an output from a delayelement 47 which delays an output from the adder circuit 46 by onesample. The adder circuit 46 generates a coefficient value K bycumulatively subtracting the cross-fading rate KS to generate acoefficient value K. The coefficient value K is directly output as thecross-fading coefficient K1, while at the same time, the same issubtracted from a value of 1 by a subtracter 48, and the resulting valueis delivered as the cross-fading coefficient K2. It should be noted thatthe cross-fading rate supply section 45 is supplied with the output fromthe adder circuit 46, i.e. the coefficient value K, and calculates avalue of K/16 based thereon to update the cross-fading rate KSR (=K/16).

The detection result signals Y, R from the level detectors 41, 42 arealso supplied via an OR gate 49 to an HT counter 50. The HT counter 50counts a time period over which the output R from the level detector 42remains inactive, and when the count or measured time period exceeds thepredetermined hold time HT, the HT counter 50 activates a cross-fadingtime (CT) counter 51 to start a counting operation. The CT counter 51counts a cross-fading time over which the DAC 2 is switched to the DAC1, and when the cross-fading time is counted up, it delivers the analogattenuation signal AT to the analog attenuator circuit 5.

To realize the above described cross-fading operation by softwareinstalled in the DSP 3, a coefficient-calculating process shown in FIG.5 may be carried out. This process will now be described in detail.

When the input digital data Di is input to the level detectors 41, 42 ofthe DSP 3, first, at a step S1, the coefficient K is set to an initialvalue of 1, a 16-step coefficient flag Fr is reset to an initial valueof 0, and a 128-step coefficient flag Fy is reset to an initial value of0. It should be noted that the 16-step coefficient flag Fr is set to 0before the cross-fading rate KS is switched from the value KSY to thevalue KSR, and to 1 after the switching, and the 128-step coefficientflag Fy is set to 0 before the cross-fading rate KS is switched from thevalue KSR to the value KSY, and to 1 after the switching.

(1) First, if the amplitude level of the input digital data Di is equalto or lower than the first threshold value TH-Y, it is determined at astep S2 that a condition of Di≧TH-R holds, and the program proceeds to astep S4, wherein it is determined whether or not the 16-step coefficientflag Fr is ON (=1). In the present case, the flag Fr is OFF (i.e.=0) bythe initialization of the process, so that the program proceeds to astep S8. If it is determined at the step S8 that a condition of Di≦TH-Yholds, the program proceeds to a step S15, where it is determinedwhether or not the 128-step coefficient flag Fy is ON (=1). In thepresent case, the flag Fy is OFF by the initialization of the process,so that the program proceeds to a step S10, wherein the cross-fadingcoefficient K1 is set to K, while the cross-fading coefficient K2 is setto 1−K. Then, the program returns to the step S2, and this loop isrepeatedly carried out and the cross-fading coefficients K1 and K2remain 1 and 0, respectively.

(2) When the amplitude level of the input digital data Di exceeds thefirst threshold value TH-Y, it is determined at the step S8 that acondition of Di>TH-Y holds, and the program proceeds to a step S9,wherein the cross-fading rate KS is set to 1/128 per step and the128-step coefficient flag Fy is set to 1 (ON). Then, the programproceeds to a step S7, wherein the coefficient K is updated to a valueof K−KS, and it is determined at the following step S11 whether or notthe coefficient K thus obtained is larger than 0. If the coefficient Kis larger than 0, the program proceeds to the step S10, wherein thecross-fading coefficients are set as described above, thereby repeatedlycarrying out the above process.

(3) When the amplitude level of the input digital data Di becomes largerthan the second threshold value TH-R, the program proceeds from the stepS2 to a step S3 to determine whether the 16-step coefficient flag Frassumes a value of 1 (ON). When this step is first carried out, the16-step coefficient flag Fr assumes a value of 0, and therefore thenegative answer is obtained at the step S3, and hence the programproceeds to a step S5, wherein the cross-fading rate KS is changed to arounded value of K/16. Further, at a step S6, the 16-step coefficientflag Fr is set to 1 (ON), and then the program proceeds to the step S7.Following the step S7, the process described above is repeatedly carriedout to update the cross-fading coefficients K1 and K2 based on thecross-fading rate KS. The cross-fading coefficients K1 and K2 thusdetermined are delivered from the cross-fading control block 16 to thecross-faders 14 and 15, respectively, to be used in the cross-fadingoperation.

(4) Once the 16-step coefficient flag Fr is set to 1, the programproceeds to the coefficient-updating process of the step S7 from thestep S3 if the input digital data Di is larger than the second thresholdvalue TH-R, and from the step S4 if the input digital data Di is equalto or smaller than the second threshold value TH-R.

(5) Further, once the 128-step coefficient flag Fy is set to 1, theprogram proceeds to the coefficient-updating process of the step S7 fromthe step S9 if the input digital data Di is larger than the firstthreshold value TH-Y, and from the step S15 if the input digital data Diis equal to or smaller than the second threshold value TH-Y.

(6) If as a result of the coefficient-updating process the coefficient Kbecomes smaller than 0, the same is set to 0 at a step S12, and the16-step coefficient flag Fr and the 128-step coefficient flag Fy areboth set to 0 (OFF) at a step S13, and then, at the following step S14,the cross-fading coefficients K1 and K2 are set to K and 1−K,respectively, followed by terminating the program.

The present invention is by no means limited to the embodiment describedabove. Although in the above embodiment, only two channels of DAC's areemployed, this is not limitative, but as shown in FIG. 6, this inventioncan be applied to an apparatus provided with a plurality of DAC's 61 ₁,61 ₂, 61 ₃, . . . , 61 _(n). A DSP 62 multiplies the input digital dataDi by factors of 1, 2^(M−N1), . . . 2^(M−Nn) (provided that 1<2^(M−N1)<. . . <2^(M−Nn)) and selects only one of outputs from the DAC's 611 to61 _(n) to be output, while digitally attenuating the unselectedoutputs. On the output side of each of the DAC's 61 ₂ to 61 _(n)′,attenuators 63 ₂, 63 ₃, . . . , 63 _(n) are arranged for converting theamplitude level of the analog signals back to their original level.These outputs and an output from the DAC 61 ₁ are added together by ananalog adder 64 and the resulting signal is output.

In this arrangement as well, when the amplitude level of the inputdigital data Di is increasing, the currently selected DAC output isprogressively and gently switched by cross-fading to another DAC outputto be selected next, while changing the cross-fading rate in dependenceon the magnitude of a change in the amplitude level of the input digitaldata. This makes it possible to reduce generation of noise whilesuppressing the amount of delay of data for processing.

Further, the amount of shift of (M−N) bits employed in the embodimentdescribed above is not limitative, but any other suitable shift amountmay be employed instead.

What is claimed is:
 1. A D/A conversion apparatus comprising: a digitalsignal processor that carries out level conversion of same input digitaldata by different conversion factors into a plurality of level-converteddigital data, selects and outputs most appropriate data of the pluralityof level-converted digital data based on a signal quality of each ofsaid plurality of level-converted digital data, outputs other data ofsaid plurality of level-converted digital data after attenuating theother data to or below a predetermined noise level, and switches betweendata previously selected as said most appropriate data and data newlyselected as said most appropriate data by carrying out cross-fadingbetween said previously selected data and said newly selected data, aplurality of D/A converters that carry out D/A conversion of saidplurality of level-converted digital data output from said digitalsignal processor to respective analog signals and outputs said analogsignals, and an analog adder device that carries out level conversion ofsaid analog signals output from said plurality of D/A converters againbased on respective corresponding ones of said conversion factors in amanner such that resulting analog signals have a level corresponding toa level of said input digital data, and then adds together all of thelevel-converted analog signals; wherein said digital signal processorcomprises: a cross-fading section that carries out cross-fading betweensaid previously selected data and said newly selected data; a delaysection that delays said input digital data by a predetermined amount ofdelay which is shorter than a time period required for completion ofsaid cross-fading carried out at a predetermined cross-fading rate bysaid cross-fading section; and a cross-fading control section thatcontrols said cross-fading section such that when an amplitude level ofsaid input digital data exceeds a predetermined threshold value, saidcross-fading section starts said cross-fading at said predeterminedcross-fading rate between said previously selected data and said newlyselected data which are delayed by said predetermined amount of delay bysaid delay section, and that when during said cross-fading a rate ofchange in said amplitude level of said input digital data, which islarger than a predetermined rate of change, is detected, saidcross-fading section carries out said cross-fading at a cross-fadingrate larger than said predetermined cross-fading rate in dependence onsaid rate of change in said amplitude level of said input digital data.2. A D/A conversion apparatus comprising: a digital signal processorthat carries out level conversion of same input digital data bydifferent conversion factors into a plurality of level-converted digitaldata, selects and outputs most appropriate data of the plurality oflevel-converted digital data based on a signal quality of each of saidplurality of level-converted digital data, outputs other data of saidplurality of level-converted digital data after attenuating the otherdata to or below a predetermined noise level, and switches between datapreviously selected as said most appropriate data and data newlyselected as said most appropriate data by carrying out cross-fadingbetween said previously selected data and said newly selected data, aplurality of D/A converters that carry out D/A conversion of saidplurality of level-converted digital data output from said digitalsignal processor to respective analog signals and outputs said analogsignals, and an analog adder device that carries out level conversion ofsaid analog signals output from said plurality of D/A converters againbased on respective corresponding ones of said conversion factors in amanner such that resulting analog signals have a level corresponding toa level of said input digital data, and then adds together all of thelevel-converted analog signals; wherein said digital signal processorcomprises: a cross-fading section that carries out cross-fading betweensaid previously selected data and said newly selected data; a delaysection that delays said input digital data by a predetermined amount ofdelay which is shorter than a time period required for completion ofsaid cross-fading carried out at a first predetermined cross-fading rateby said cross-fading section; and a cross-fading control section thatcontrols said cross-fading section such that when an amplitude level ofsaid input digital data exceeds a first predetermined threshold value,said cross-fading section starts said cross-fading at said firstpredetermined cross-fading rate between said previously selected dataand said newly selected data which are delayed by said predeterminedamount of delay by said delay section, and that when during saidcross-fading said amplitude level of said input digital data exceeds asecond predetermined threshold value larger than said firstpredetermined threshold value, said cross-fading section carries outsaid cross-fading at a second predetermined cross-fading rate largerthan said first predetermined cross-fading rate.
 3. A D/A conversionapparatus according to claim 2, wherein said second predeterminedthreshold value is set to a limit of said amplitude level of said inputdigital data beyond which an overflow occurs when level conversion iscarried out on said input digital data by a corresponding one of saiddifferent conversion factors, and said second cross-fading rate is setsuch that said cross-fading is completed in a time period correspondingto said predetermined amount of delay provided by said delay section. 4.A D/A conversion apparatus according to claim 2, wherein saidcross-fading is carried out using a cross-fading coefficient, said timeperiod required for completion of said cross-fading carried out at saidfirst predetermined cross-fading rate is a time period required forprocessing of N1 samples of said input digital data, and saidpredetermined amount of delay provided by said delay section correspondsto a time period required for processing of N2 samples of said inputdigital data (N1>N2), and wherein said cross-fading coefficient isincremented/decremented by 1/N1 for each step of said cross-fading,after said amplitude level of said input digital data exceeds said firstthreshold value and before said amplitude level of said input digitaldata exceeds said second predetermined threshold value, and saidcross-fading coefficient is incremented/decremented by (1−K)/N2 for eachstep of said cross-fading, after said amplitude level of said inputdigital data exceeds said second predetermined threshold value, whereinK represents a value of said cross-fading coefficient assumed at a timepoint said amplitude level of said input digital data exceeds saidsecond threshold value.
 5. A D/A conversion apparatus according to claim3, wherein said cross-fading is carried out using a cross-fadingcoefficient, said time period required for completion of saidcross-fading carried out at said first predetermined cross-fading rateis a time period required for processing of N1 samples of said inputdigital data, and said predetermined amount of delay provided by saiddelay section corresponds to a time period required for processing of N2samples of said input digital data (N1>N2), and wherein saidcross-fading coefficient is incremented/decremented by 1/N1 for eachstep of said cross-fading, after said amplitude level of said inputdigital data exceeds said first threshold value and before saidamplitude level of said input digital data exceeds said secondpredetermined threshold value, and said cross-fading coefficient isincremented/decremented by (1−K)/N2 for each step of said cross-fading,after said amplitude level of said input digital data exceeds saidsecond predetermined threshold value, wherein K represents a value ofsaid cross-fading coefficient assumed at a time point said amplitudelevel of said input digital data exceeds said second threshold value. 6.A D/A conversion method comprising the steps of: delaying input digitaldata by a predetermined amount of delay which is shorter than a timeperiod required for completion of cross-fading carried out at apredetermined cross-fading rate; carrying out level conversion of saiddelayed input digital data by different conversion factors into aplurality of level-converted digital data; selecting and outputting mostappropriate data of said plurality of level-converted digital data basedon a signal quality of each of said plurality of level-converted digitaldata, and outputting other data of said plurality of level-converteddigital data after attenuating said other data to or below apredetermined noise level; switching between data previously selected assaid most appropriate data of said plurality of level-converted digitaldata and data newly selected as said most appropriate data by carryingout said cross-fading between said previously selected data and saidnewly selected data; carrying out D/A conversion of said plurality oflevel-converted digital data to respective analog signals and outputtingsaid analog signals; and carrying out level conversion of said analogsignals again based on respective corresponding ones of said conversionfactors in a manner such that resulting analog signals have a levelcorresponding to a level of said input digital data, and then addingtogether all of the level-converted analog signals; wherein when anamplitude level of said input digital data exceeds a predeterminedthreshold value, said cross-fading is started between said previouslyselected data and said newly selected data which are delayed by saidpredetermined amount of delay, and when during said cross-fading a rateof change in said amplitude level of said input digital data, which islarger than a predetermined rate of change, is detected, saidcross-fading is carried out at a cross-fading rate larger than saidpredetermined cross-fading rate in dependence on said rate of change insaid amplitude level of said input digital data.
 7. A D/A conversionmethod comprising the steps of: delaying input digital data by apredetermined amount of delay which is shorter than a time periodrequired for completion of cross-fading carried out at a firstpredetermined cross-fading rate; carrying out level conversion of saiddelayed input digital data by different conversion factors into aplurality of level-converted digital data; selecting and outputting mostappropriate data of said plurality of level-converted digital data basedon a signal quality of each of said plurality of level-converted digitaldata, and outputting other data of said plurality of level-converteddigital data after attenuating said other data to or below apredetermined noise level; switching between data previously selected assaid most appropriate data of said plurality of level-converted digitaldata and data newly selected as said most appropriate data by carryingout said cross-fading between said previously selected data and saidnewly selected data; carrying out D/A conversion of said plurality oflevel-converted digital data to respective analog signals and outputtingsaid analog signals; and carrying out level conversion of said analogsignals again based on respective corresponding ones of said conversionfactors in a manner such that resulting analog signals have a levelcorresponding to a level of said input digital data, and then addingtogether all of the level-converted analog signals; wherein when anamplitude level of said input digital data exceeds a first predeterminedthreshold value, said cross-fading is started at said firstpredetermined cross-fading rate between said previously selected dataand said newly selected data which are delayed by said predeterminedamount of delay, and when during said cross-fading said amplitude levelof said input digital data exceeds a second predetermined thresholdvalue larger than said first predetermined threshold value, saidcross-fading is carried out at a second predetermined cross-fading ratelarger than said first predetermined cross-fading rate.